1. Field of the Invention
The present invention relates to a polishing slurry used for a chemical mechanical polishing (CMP) process, and more particularly, to a polishing slurry which allows for control of removal rates of a silicon oxide layer and a silicon nitride layer exposed during polishing of a polysilicon layer.
2. Description of the Related Art
Semiconductor devices are comprised of numerous integrated circuits, which are produced by selectively and repeatedly performing a series of photographic, etching, diffusive, metal deposition, and other process steps. For example, plasma enhanced-chemical vapor deposition (PE-CVD) processes and reactive ion etch (RIE) processes are used to fully form device patterns that are pre-set on the wafer.
During the semiconductor device manufacturing process, a chemical mechanical polishing (CMP) process is typically used for horizontally planarizing various kinds of layers, such as oxide layers, nitride layers, metal layers and the like, which are sequentially deposited on the semiconductor wafer to form the integrated circuits.
A typical CMP apparatus includes a polishing table used for supporting and rotating a CMP pad positioned on the table. A wafer confronting the pad is fixed and rotated by a carrier positioned above the table, which carrier moves vertically to selectively contact the wafer and the CMP pad at a designated pressure. The CMP pad is also rotated at the same time by the polishing table. A slurry mixture, which comprises a mixture of predetermined types of chemicals and other ingredients, is usually provided at the central point of the CMP pad, and is then evenly distributed and coated on the upper surface of the CMP pad by the rotating force of the CMP pad. The semiconductor wafer attached to the wafer carrier selectively contacts the slurry covered CMP pad to carry out the CMP process.
As a result of the relative rotation between the wafer and the CMP pad, and the slurry mixture on the surface of the CMP pad, both mechanical friction and chemical reactions take place, and the material comprising the layer to be polished is gradually removed from the surface of the wafer. More specifically, the mechanical removing action is performed by polishing particles within the polishing slurry and surface bosses of the pad, and a chemical removing action is performed by a chemical ingredient within the polishing slurry. As a result, a wafer is said to be planarized to a certain pre-set thickness on the surface of the wafer.
It is well known that the ultimate quality of the polished state of a wafer depends on several factors, including, among others: (i) the mechanical friction between the CMP pad and the wafer, (ii) the material and state of the CMP pad, (iii) the evenness or uniformity of the surface of the CMP pad, and (iv) the distribution rate and composition of the chemical slurry. This disclosure is mainly directed to the composition of the chemical slurry.
In one particular patterning example, self-aligned contact holes are formed within an inter-silicon oxide layer interposed between a bit line and a semiconductor substrate, or between a storage electrode and a semiconductor substrate, in order to form a plug for connecting the bit line or the storage electrode to an active region of the semiconductor substrate. After filling up the contact holes with a polysilicon layer, a partial CMP process is performed until the surface of the inter-silicon oxide layer is exposed. However, in this example, a problem exists in that the thickness of the inter-silicon oxide layer is not uniform after the partial CMP, which in turn causes additional problems after a full CMP is performed.
FIGS. 1 through 3 illustrate a full conventional CMP process. Referring to FIG. 1, a plurality of gate electrode structures (G1, G2, G3, G4, G5, G6, and G7) are formed on a semiconductor substrate 10. The respective gate electrode structures are comprised of a gate dielectric layer 12, a polysilicon layer 14, a metal silicide layer 16, and a capping layer 18, which are sequentially formed, and a spacer 20 formed on the side walls thereof. An inter-dielectric layer 22 is formed on the entire surface of the semiconductor substrate 10 having the gate electrode structures. The capping layer 18 and the spacer 20 are formed of a material having a greater etching selectivity relative to the inter-dielectric layer 22. The inter-dielectric layer 22 is generally formed of a silicon oxide, and the capping layer 18 and the spacer 20 are formed of a silicon nitride.
After forming a mask 24 on a predetermined portion of the inter-dielectric layer 22, the inter-dielectric layer 22 is etched (using dry etching for example), and contact holes 19 are formed between the gate electrode structures G2 and G3, between the gate electrode structures G3 and G4, and between the gate electrode structures G4 and G5.
During the process for forming the contact holes 19, portions of the capping layer 18 are damaged (i.e., overetched), such as damaged portions 18a of the capping layer of the gate electrode structures G2, G3, G4, G5. The damage results in the capping layer 18a being thinner at the gate electrode structures G2, G3, G4, G5, as compared the thickness of the capping layer 18 of the gate electrode structures G1, G6, G7 under the mask 24.
In FIG. 2, after removing the mask 24, a polysilicon layer 26 is formed on the entire surface of the inter-dielectric layer 22 including the contact holes.
Next, a CMP is performed on the polysilicon layer 26. Since the capping layer 18 of the gate electrode structures G1, G6, G7 is thicker than the capping layer 18a of the gate electrode structures G2, G3, G4, G5 disposed in a region where a plug will be formed, the CMP process stops when it reaches the upper surface of the capping layer 18. Therefore, as shown in FIG. 3, the plug 26a not only fills up the contact holes, but it also has a sufficient layer thickness to “connect” each of the contact holes, even after the CMP process is completed. In other words, the contact holes are not “separated”, which can cause shorts unless corrected.
The polishing slurry composition used (see Table 1) has a large removal rate to the silicon oxide layer and the silicon nitride layer, so that if the additional CMP process is performed to separate the plug 26a using this typical polishing slurry, the capping layers 18, 18a of the upper portion of the gate electrode structures become completely removed, and the gate electrodes become damaged.
TABLE 1Conventional Polishing Slurry Selectivity RatesSelectivitySelectivityPE-TEOSSi3N4Polysilicon(PE-TEOS:(PE-TEOS:(Å/minute) (Å/minute)(Å/minute)Si3N4)polysilicon)250158860344.250.41
Table 1 shows the selectivity when a polysilicon layer, a silicon oxide layer (PE-TEOS), and a silicon nitride layer (Si3N4), are simultaneously polished, in accordance with the following process conditions. The polishing slurry includes the well known ss-25 base polishing slurry and a fumed silica manufactured by the Cabot Co., which is diluted with deionized water at a ratio of 1:1. The downward force of a polishing head of a polisher manufactured by the Presi Co. is set at 5 psi, and the speed of the polishing table is set at 65 rpm.
As shown in Table 1, since the removal rates of the silicon oxide layer and the silicon nitride layer, which are removed together during the removal of the polysilicon layer, are large, the probability is high that the gate electrodes will be damaged, and it is thus difficult to secure a CMP process margin of the polysilicon layer.
Therefore, to counter this overetching tendency, the capping layer 18 of the gate electrode structures are formed rather thick, which takes into consideration the additional CMP process margin needed to separate the polysilicon plug 26a as described above in FIG. 3. However, this increases the cost and time to produce a device.
Therefore, a need exists for a polishing slurry which exhibits a high removal rate for the polysilicon layer, while exhibiting a much lower removal rate for the silicon oxide layer and the silicon nitride layer.